SH7046 Datasheet, PDF (144/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 7 User Break Controller (UBC)
7.4 Examples of Use
Break on CPU Instruction Fetch Cycle
1. Register settings: UBARH = H'0000
UBARL = H'0404
UBBR = H'0054
UBCR = H'0000
Conditions set: Address: H'00000404
Bus cycle: CPU, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled
A user break interrupt will occur before the instruction at address H'00000404. If it is possible
for the instruction at H'00000402 to accept an interrupt, the user break exception processing
will be executed after execution of that instruction. The instruction at H'00000404 is not
executed. The PC value saved is H'00000404.
2. Register settings: UBARH = H'0015
UBARL = H'389C
UBBR = H'0058
UBCR = H'0000
Conditions set:
Address: H'0015389C
Bus cycle: CPU, instruction fetch, write
(operand size is not included in conditions)
Interrupt requests enabled
A user break interrupt does not occur because the instruction fetch cycle is not a write cycle.
3. Register settings: UBARH = H'0003
UBARL = H'0147
UBBR = H'0054
UBCR = H'0000
Conditions set: Address: H'00030147
Bus cycle: CPU, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled
A user break interrupt does not occur because the instruction fetch was performed for an even
address. However, if the first instruction fetch address after the branch is an odd address set by
these conditions, user break interrupt exception processing will be carried out after address
error exception processing.
Rev. 4.00 Dec 05, 2005 page 100 of 564
REJ09B0270-0400