SH7046 Datasheet, PDF (446/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
Initial
Bit Bit Name Value R/W Description
1
MD1
0
R/W Mode 0 to 3
0
MD0
0
R/W These bits set the timer operating mode.
00: Operation halted
01: Operating mode 1 (Transfer at TCNT = TPDR)
10: Operating mode 2 (Transfer at TCNT = TDDR × 2)
11: Operating mode 3 (Transfer at TCNT = TPDR or
TCNT = TDDR × 2)
15.3.2 Timer Control Register (TCNR)
The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects
the enabling or disabling of register access, and selects counter operation or halting.
Initial
Bit Bit Name Value R/W Description
7
TTGE
0
R/W A/D Start-Conversion request Enable
Enables or disables the generation of A/D start-
conversion requests when the TGFN or TGFM bit of the
timer status register (TSR) is set.
0: Disables request
1: Enables request
6
CST
0
R/W Timer Counter Start
Selects operation or halting of the timer counter (TCNT)
and timer dead time counter (TDCNT).
0: TCNT and TDCNT operation is halted
1: TCNT and TDCNT perform count operations
5
RPRO
0
R/W Register Protects
Enables or disables the reading of registers other than
TSR, and enables or disables the writing to registers
other than TBRU to TBRW, TPBR, and TSR. Writes to
TCNR itself are also disabled. Note that reset input is
necessary in order to write to these registers again.
0: Register access enabled
1: Register access disabled
Rev. 4.00 Dec 05, 2005 page 402 of 564
REJ09B0270-0400