SH7046 Datasheet, PDF (67/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Instruction Formats
d format
15
0
xxxx xxxx dddd dddd
d12 format
15
xxxx dddd
dddd
0
dddd
Source
Operand
Destination
Operand
Example
dddddddd: Indirect R0 (Direct register) MOV.L
GBR with
@(disp,GBR),R0
displacement
R0 (Direct register) dddddddd: Indirect MOV.L
GBR with
R0,@(disp,GBR)
displacement
dddddddd: PC
relative with
displacement


R0 (Direct register) MOVA
@(disp,PC),R0
dddddddd: PC
relative
dddddddddddd:
PC relative
BF
label
BRA label
(label = disp
+ PC)
nd8 format
15
xxxx nnnn
dddd
0
dddd
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
i format
iiiiiiii: Immediate
15
0
xxxx xxxx i i i i i i i i
iiiiiiii: Immediate
iiiiiiii: Immediate
ni format
iiiiiiii: Immediate
15
0
xxxx nnnn i i i i i i i i
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
R0 (Direct register) AND #imm,R0

TRAPA #imm
nnnn: Direct
register
ADD #imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 4.00 Dec 05, 2005 page 23 of 564
REJ09B0270-0400