SH7046 Datasheet, PDF (42/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Table 12.10 SCI Interrupt Sources ............................................................................................. 365
Section 13 A/D Converter
Table 13.1 Pin Configuration ................................................................................................... 371
Table 13.2 Channel Select List................................................................................................. 374
Table 13.3 A/D Conversion Time (Single Mode) .................................................................... 380
Table 13.4 A/D Conversion Time (Scan Mode)....................................................................... 380
Table 13.5 A/D Converter Interrupt Source ............................................................................. 381
Table 13.6 Analog Pin Specifications ...................................................................................... 386
Section 15 Motor Management Timer (MMT)
Table 15.1 Pin Configuration ................................................................................................... 399
Table 15.2 Initial Values of TBRU to TBRW and Initial Output............................................. 412
Table 15.3 Relationship between A/D Conversion Start Timing and Operating Mode ........... 415
Table 15.4 MMT Interrupt Sources.......................................................................................... 416
Table 15.5 Pin Configuration ................................................................................................... 427
Section 16 Pin Function Controller (PFC)
Table 16.1 Multiplexed Pins (Port A) ...................................................................................... 433
Table 16.2 Multiplexed Pins (Port B)....................................................................................... 434
Table 16.3 Multiplexed Pins (Port E)....................................................................................... 434
Table 16.4 Multiplexed Pins (Port F) ....................................................................................... 435
Table 16.5 Multiplexed Pins (Port G) ...................................................................................... 435
Table 16.6 Pin Functions in Each Mode .................................................................................. 436
Section 17 I/O Ports
Table 17.1 Port A Data Register L (PADRL) Read/Write Operations..................................... 451
Table 17.2 Port B Data Register (PBDR) Read/Write Operations ........................................... 452
Table 17.3 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations..... 455
Table 17.4 Port F Data Register (PFDR) Read/Write Operations............................................ 457
Table 17.5 Port G Data Register (PGDR) Read/Write Operations........................................... 458
Section 18 Flash Memory (F-ZTAT Version)
Table 18.1 Differences between Boot Mode and User Program Mode.................................... 461
Table 18.2 Pin Configuration ................................................................................................... 465
Table 18.3 Setting On-Board Programming Modes................................................................. 470
Table 18.4 Boot Mode Operation............................................................................................. 472
Table 18.5 Peripheral Clock (Pφ) Frequencies for which Automatic Adjustment of LSI Bit
Rate is Possible....................................................................................................... 472
Rev. 4.00 Dec 05, 2005 page xlii of xliv