SH7046 Datasheet, PDF(41/611 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

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SH7046 Datasheet, PDF (41/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

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Table 10.27 Output Level Select Function................................................................................. 174

Table 10.28 Output level Select Function .................................................................................. 176

Table 10.29 Register Combinations in Buffer Operation........................................................... 186

Table 10.30 Cascaded Combinations ......................................................................................... 189

Table 10.31 PWM Output Registers and Output Pins................................................................ 192

Table 10.32 Phase Counting Mode Clock Input Pins................................................................. 196

Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... 197

Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... 198

Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... 199

Table 10.36 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 200

Table 10.37 Output Pins for Reset-Synchronized PWM Mode ................................................. 203

Table 10.38 Register Settings for Reset-Synchronized PWM Mode ......................................... 203

Table 10.39 Output Pins for Complementary PWM Mode........................................................ 207

Table 10.40 Register Settings for Complementary PWM Mode................................................ 208

Table 10.41 Registers and Counters Requiring Initialization..................................................... 216

Table 10.42 MTU Interrupts ...................................................................................................... 234

Table 10.43 Mode Transition Combinations.............................................................................. 262

Table 10.44 Pin Configuration ................................................................................................... 295

Table 10.45 Pin Combinations ................................................................................................... 295

Section 11 Watchdog Timer

Table 11.1 Pin Configuration ................................................................................................... 304

Table 11.2 WDT Interrupt Source (in Interval Timer Mode)................................................... 313

Section 12 Serial Communication Interface (SCI)

Table 12.1 Pin Configuration ................................................................................................... 319

Table 12.2 Relationships between N Setting in BRR and Effective Bit Rate B0...................... 328

Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 329

Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. 330

Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. 331

Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. 332

Table 12.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator

(Asynchronous Mode)............................................................................................ 333

Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 334

Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1)................. 335

Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)................. 336

Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3)................. 337

Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4)................. 338

Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 339

Table 12.8 Serial Transfer Formats (Asynchronous Mode) ..................................................... 341

Table 12.9 SSR Status Flags and Receive Data Handling........................................................ 348

Rev. 4.00 Dec 05, 2005 page xli of xliv

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