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MC9S12G Datasheet, PDF (987/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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192 KByte Flash Module (S12FTMRG192K2V1)
27.3.2.9.1 P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 27-21 speciï¬es
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reï¬ect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
Table 27-21. P-Flash Protection Scenario Transitions
From
To Protection Scenario1
Protection
Scenario
0
1
2
3
4
5
6
7
0
X
X
X
X
1
X
X
2
X
X
3
X
4
X
X
5
X
X
X
X
6
X
X
X
X
7
X
X
X
X
X
X
X
X
1 Allowed transitions marked with X, see Figure 27-14 for a deï¬nition of the scenarios.
27.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register deï¬nes which EEPROM sectors are protected against program and erase operations.
Offset Module Base + 0x0009
7
6
5
4
3
2
1
0
R
DPOPEN
W
DPS[6:0]
Reset
F1
F1
F1
F1
F1
F1
F1
F1
Figure 27-15. EEPROM Protection Register (EEPROT)
1 Loaded from IFR Flash conï¬guration ï¬eld, during reset sequence.
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, ï¬elds DPOPEN and DPS of the EEPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
987
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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