MC9S12G Datasheet, PDF (645/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Timer Module (TIM16B8CV3)
Read: Anytime
Write: Anytime.
Table 20-13. TIE Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field
7:0
C7I:C0I
Description
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
20.3.2.11 Timer System Control Register 2 (TSCR2)
7
6
5
4
3
2
1
0
R
0
0
0
TOI
TCRE
PR2
PR1
PR0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-19. Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Table 20-14. TSCR2 Field Descriptions
Field
7
TOI
3
TCRE
2
PR[2:0]
Description
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1,
TOF will never be set when TCNT is reset from 0xFFFF to 0x0000.
Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for
a more detail explanation please refer to Section 20.4.3, “Output Compare
Note: This bit and feature is available only when channel 7 exists. If channel 7 doesn’t exist, this bit is reserved.
Writing to reserved bit has no effect. Read from reserved bit return a zero.
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 20-15.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
645
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.