MC9S12G Datasheet, PDF (309/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
Mode
Table 8-36. Trace Buffer Organization (Normal,Loop1,Detail modes)
Entry
Number
4-bits
Field 2
8-bits
Field 1
8-bits
Field 0
Detail Mode
Entry 1
Entry 2
CINF1,ADRH1
0
CINF2,ADRH2
0
Normal/Loop1 ^{Entry 1}
Modes
Entry 2
PCH1
PCH2
ADRM1
DATAH1
ADRM2
DATAH2
PCM1
PCM2
ADRL1
DATAL1
ADRL2
DATAL2
PCL1
PCL2
8.4.5.3.1 Information Bit Organization
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
Bit 3
CSZ
Bit 2
CRW
Bit 1
Bit 0
ADDR[17] ADDR[16]
Figure 8-25. Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Table 8-37. Field Descriptions
Bit
Description
3
CSZ
Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode
0 Word Access
1 Byte Access
2
CRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access when tracing in Detail Mode.
0 Write Access
1 Read Access
1
Address Bus bit 17— Corresponds to system address bus bit 17.
ADDR[17]
0
Address Bus bit 16— Corresponds to system address bus bit 16.
ADDR[16]
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
309
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.