MC9S12G Datasheet, PDF (195/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.4.3.44 Port J Data Direction Register (DDRJ)
Address 0x026A (G1, G2)
7
R
DDRJ7
W
Reset
0
Address 0x026A (G3)
6
DDRJ6
0
5
DDRJ5
0
4
DDRJ4
0
3
DDRJ3
0
2
DDRJ2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
DDRJ3
DDRJ2
0
0
0
0
0
Figure 2-44. Port J Data Direction Register (DDRJ)
Access: User read/write¹
1
0
DDRJ1
DDRJ0
0
0
Access: User read/write¹
1
0
DDRJ1
DDRJ0
0
0
Table 2-71. DDRJ Register Field Descriptions
Field
7-0
DDRJ
Description
Port J data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.45 Port J Pull Device Enable Register (PERJ)
Address 0x026C (G1, G2)
7
R
PERJ7
W
Reset
1
Address 0x026C (G3)
6
PERJ6
1
5
PERJ5
1
4
PERJ4
1
3
PERJ3
1
2
PERJ2
1
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
PERJ3
PERJ2
0
0
0
1
1
Figure 2-45. Port J Pull Device Enable Register (PERJ)
Access: User read/write¹
1
0
PERJ1
PERJ0
1
1
Access: User read/write¹
1
0
PERJ1
PERJ0
1
1
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
195
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.