MC9S12G Datasheet, PDF (574/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Serial Communication Interface (S12SCIV5)
BERRM1
1
Table 18-9. Bit Error Mode Coding
BERRM0
1
Reserved
Function
18.3.2.6 SCI Control Register 2 (SCICR2)
Module Base + 0x0003
7
R
TIE
W
Reset
0
6
5
4
3
2
TCIE
RIE
ILIE
TE
RE
0
0
0
0
0
Figure 18-9. SCI Control Register 2 (SCICR2)
1
RWU
0
0
SBK
0
Read: Anytime
Write: Anytime
Table 18-10. SCICR2 Field Descriptions
Field
7
TIE
6
TCIE
5
RIE
4
ILIE
3
TE
2
RE
Description
Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate
interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate
interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag,
OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by
the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
Receiver Enable Bit — RE enables the SCI receiver.
0 Receiver disabled
1 Receiver enabled
MC9S12G Family Reference Manual, Rev.1.01
574
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.