MC9S12G Datasheet, PDF (197/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.4.3.47 Port J Interrupt Enable Register (PIEJ)
Read: Anytime
Address 0x026E (G1, G2)
7
R
PIEJ7
W
Reset
0
Address 0x026E (G3)
6
PIEJ6
0
5
PIEJ5
0
4
PIEJ4
0
3
PIEJ3
0
2
PIEJ2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
PIEJ3
PIEJ2
0
0
0
0
0
Figure 2-47. Port J Interrupt Enable Register (PIEJ)
Access: User read/write¹
1
0
PIEJ1
PIEJ0
0
0
Access: User read/write¹
1
0
PIEJ1
PIEJ0
0
0
Field
7-0
PIEJ
Table 2-74. PIEJ Register Field Descriptions
Description
Port J interrupt enable—
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
2.4.3.48 Port J Interrupt Flag Register (PIFJ)
Address 0x026F (G1, G2)
7
R
PIFJ7
W
Reset
0
Address 0x026F (G3)
6
PIFJ6
0
5
PIFJ5
0
4
PIFJ4
0
3
PIFJ3
0
2
PIFJ2
0
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
PIFJ3
PIFJ2
0
0
0
0
0
Figure 2-48. Port J Interrupt Flag Register (PIFJ)
Access: User read/write¹
1
0
PIFJ1
PIFJ0
0
0
Access: User read/write¹
1
0
PIFJ1
PIFJ0
0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
197
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.