MC9S12G Datasheet, PDF (297/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
8.3.2.8.4 Debug Comparator Address Low Register (DBGXAL)
Address: 0x002B
R
W
Reset
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
Figure 8-18. Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See Table 8-23 for visible register encoding.
Write: If DBG not armed. See Table 8-23 for visible register encoding.
Table 8-26. DBGXAL Field Descriptions
Field
7–0
Bits[7:0]
Description
Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the
selected comparator compares the address bus bits [7:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
8.3.2.8.5 Debug Comparator Data High Register (DBGADH)
Address: 0x002C
R
W
Reset
7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
0
Bit 8
0
Figure 8-19. Debug Comparator Data High Register (DBGADH)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
Table 8-27. DBGADH Field Descriptions
Field
Description
7–0
Bits[15:8]
Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
297
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.