MC9S12G Datasheet, PDF (233/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Chapter 5
S12G Memory Map Controller (S12GMMCV1)
Rev. No.
Date
(Item No.) (Submitted By)
01.02
01.03
01.04
20-May 2010
26-Jul 2010
20-Aug 2010
Table 5-1. Revision History Table
Sections
Affected
Substantial Change(s)
Updates for S12VR48 and S12VR64
5.1 Introduction
The S12GMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources. Figure 5-1 shows a block diagram of the S12GMMC module.
5.1.1 Glossary
Term
Local Addresses
Global Address
Aligned Bus Access
Misaligned Bus Access
NS
SS
Unimplemented Address Ranges
NVM
IFR
Table 5-2. Glossary Of Terms
Definition
Address within the CPU12’s Local Address Map (Figure 5-11)
Address within the Global Address Map (Figure 5-11)
Bus access to an even address.
Bus access to an odd address.
Normal Single-Chip Mode
Special Single-Chip Mode
Address ranges which are not mapped to any on-chip resource.
Non-volatile Memory; Flash or EEPROM
NVM Information Row. Refer to FTMRG Block Guide
5.1.2 Overview
The S12GMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources
(memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps.
Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for
selecting the MCU’s functional mode.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
233
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.