MC9S12G Datasheet, PDF (1082/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Electrical Characteristics
2 _{Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.J}
3 _{Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.}
4 _{.Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured in}
simulation on the top surface of the board near the package.
5 _{Thermal resistance between the die and the case top surface as measured in simulation by the cold plate method (MIL}
SPEC-883 Method 1012.1).
6 _{Thermal characterization parameter indicating the temperature difference between package top and the junction temperature}
per JEDEC JESD51-2. Ψ_JT is a useful value to use to estimate junction temperature in a steady state customer enviroment.
A.2 I/O Characteristics
This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST, and supply pins.
Table A-6. 3.3-V I/O Characteristics
ALL 3.3V RANGE I/O PARAMETERS ARE SUBJECT TO CHANGE FOLLOWING CHARACTERIZATION
Conditions are 3.15 V < V_DD35 < 3.6 V junction temperature from –40°C to +150°C, unless otherwise noted
I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins.
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 P Input high voltage
V_IH
0.65V*V_DD35
—
—
V
2 T Input high voltage
V_IH
—
—
V_DD35+0.3
V
3 P Input low voltage
V_IL
—
—
0.35*V_DD35 V
4 T Input low voltage
V_IL
V_SS35 – 0.3
—
—
V
5 C Input hysteresis
V_HYS
0.06V*V_DD35
—
0.3V*V_DD35 mV
6
Input leakage current (pins in high impedance input
mode)¹ Vin = VDD35 or VSS35
I_in
P M temperature range
-1
—
V temperature range
-0.5
—
C temperature range
-0.4
—
µA
1
0.5
0.4
7 C Input leakage current (pins in high impedance input
mode)¹ Vin = VDD35 or VSS35
I_in
27°C
µA
1
8 P Output high voltage (pins in output mode)
IOH = –1.75 mA
V_OH
V_DD35-0.4
—
9 C Output low voltage (pins in output mode)
IOL = +1.75 mA
V_OL
—
—
10 P Internal pull up device current
V_IH min > input voltage > V_IL max
I_PUL
-1
—
11 P Internal pull down device current
V_IH min > input voltage > V_IL max
I_PDH
1
—
12 D Input capacitance
C_in
—
7
13 T Injection current²
—
Single pin limit
Total device limit, sum of all injected currents
I_ICS
–2.5
I_ICP
–25
14 P Port J, P, AD interrupt input pulse filtered (STOP)³
t_{P_MASK}
—
—
15 P Port J, P, AD interrupt input pulse passed (STOP)³
t_{P_PASS}
10
—
—
V
0.4
V
–70
µA
70
µA
—
pF
mA
2.5
25
3
µs
—
µs
MC9S12G Family Reference Manual, Rev.1.01
1082
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.