MC9S12G Datasheet, PDF (340/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
0x0037
7
R
RTIF
W
6
PORF
5
LVRF
4
LOCKIF
3
LOCK
2
ILAF
1
OSCIF
0
UPOSC
Reset
0
Note 1
Note 2
0
0
Note 3
0
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
= Unimplemented or Reserved
Figure 10-7. S12CPMU Flags Register (CPMUFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 10-3. CPMUFLG Field Descriptions
Field
7
RTIF
6
PORF
5
LVRF
4
LOCKIF
3
LOCK
2
ILAF
Description
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
Lock Status Bit — LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL is
unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL
stabilization time tlock.
0 VCOCLK is not within the desired tolerance of the target frequency.
f_PLL = f_VCO/4.
1 VCOCLK is within the desired tolerance of the target frequency.
f_PLL = f_VCO/(POSTDIV+1).
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for
details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
MC9S12G Family Reference Manual, Rev.1.01
340
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.