MC9S12G Datasheet, PDF (418/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B12CV2)
12.4.2 Digital Sub-Block
This subsection describes some of the digital features in more detail. See Section 12.3.2, “Register
Descriptions” for all details.
12.4.2.1 External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to an external event rather
than relying only on software to trigger the ATD module when a conversions is about to take place. The
external trigger signal (out of reset ATD channel 11, configurable in ATDCTL1) is programmable to be
edge or level sensitive with polarity control. Table 12-23 gives a brief description of the different
combinations of control bits and their effect on the external trigger function.
ETRIGLE
X
X
0
0
1
1
Table 12-23. External Trigger Control Bits
ETRIGP
X
X
0
1
0
1
ETRIGE
0
0
1
1
1
1
SCAN
Description
0
Ignores external trigger. Performs one
conversion sequence and stops.
1
Ignores external trigger. Performs
continuous conversion sequences.
X
Trigger falling edge sensitive. Performs
one conversion sequence per trigger.
X
Trigger rising edge sensitive. Performs one
conversion sequence per trigger.
X
Trigger low level sensitive. Performs
continuous conversions while trigger level
is active.
X
Trigger high level sensitive. Performs
continuous conversions while trigger level
is active.
In either level or edge sensitive modes, the first conversion begins when the trigger is received.
Once ETRIGE is enabled a conversion must be triggered externally after writing to ATDCTL5 register.
During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error flag
ETORF is set.
If level sensitive mode is active and the external trigger de-asserts and later asserts again during a
conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left
active in level sensitive mode when a sequence is about to complete, another sequence will be triggered
immediately.
MC9S12G Family Reference Manual, Rev.1.01
418
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.