MC9S12G Datasheet, PDF (668/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

16 KByte Flash Module (S12FTMRG16K1V1)
Address
& Name
7
6
5
4
3
2
1
0
0x0011
R
0
0
0
0
0
0
0
0
FRSV5 _W
0x0012
R
0
0
0
0
0
0
0
0
FRSV6 _W
0x0013
R
0
0
0
0
0
0
0
0
FRSV7 _W
= Unimplemented or Reserved
Figure 21-4. FTMRG16K1 Register Summary (continued)
21.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIVLCK
FDIV[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
Table 21-7. FCLKDIV Field Descriptions
Field
7
FDIVLD
Description
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
MC9S12G Family Reference Manual, Rev.1.01
668
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.