MC9S12G Datasheet, PDF (537/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

17.3 Memory Map and Register Definition
Pulse-Width Modulator (S12PWM8B8CV2)
17.3.1 Module Memory Map
This section describes the content of the registers in the scalable PWM module. The base address of the
scalable PWM module is determined at the MCU level when the MCU is defined. The register decode map
is fixed and begins at the first address of the module address offset. The figure below shows the registers
associated with the scalable PWM and their relative offset from the base address. The register detail
description follows the order they appear in the register map.
Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented
functions are indicated by shading the bit.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
17.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the scalable PWM module.
Register
Name
Bit 7
PWME¹
R
PWME7
W
PWMPOL¹ R
W
PPOL7
PWMCLK¹ R
W
PCLK7
6
PWME6
PPOL6
PCLKL6
5
PWME5
PPOL5
PCLK5
4
PWME4
PPOL4
PCLK4
3
PWME3
PPOL3
PCLK3
2
PWME2
PPOL2
PCLK2
1
PWME1
PPOL1
PCLK1
Bit 0
PWME0
PPOL0
PCLK0
PWMPRCLK R
0
W
PWMCAE¹ R
W
CAE7
PWMCTL¹ R
CON67
W
PCKB2
CAE6
CON45
PCKB1
CAE5
CON23
PCKB0
CAE4
CON01
0
CAE3
PSWAI
PCKA2
CAE2
PFRZ
PCKA1
CAE1
0
PCKA0
CAE0
0
PWMCLKAB R
1
PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0
W
= Unimplemented or Reserved
Figure 17-2. The scalable PWM Register Summary (Sheet 1 of 4)
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
537
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.