MC9S12G Datasheet, PDF (338/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
Reserved
VCOFRQ[1:0]
11
10.3.2.2 S12CPMU Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
0x0035
7
6
5
4
3
2
1
0
R
REFFRQ[1:0]
W
0
0
REFDIV[3:0]
Reset
0
0
0
0
1
1
1
1
Figure 10-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
If XOSCLCP is enabled (OSCE=1)
If XOSCLCP is disabled (OSCE=0)
f _REF = ₍---_R----_E----_F-^f--^OD-----^SI--_V-^C-----₊-----₁---₎-
fREF = fIRC1M
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Table 10-2.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f_REF <=
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
MC9S12G Family Reference Manual, Rev.1.01
338
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.