MC9S12G Datasheet, PDF (389/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B8CV2)
Module Base + 0x0006
R
W
Reset
7
SCF
0
6
5
4
3
2
1
0
0
CC3
CC2
CC1
CC0
ETORF
FIFOR
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime
Write: Anytime (No effect on (CC3, CC2, CC1, CC0))
Table 11-16. ATDSTAT0 Field Descriptions
Field
7
SCF
5
ETORF
4
FIFOR
3–0
CC[3:0]
Description
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared
when one of the following occurs:
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and a result register is read
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
A) Write “1” to ETORF
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No External trigger overrun error has occurred
1 External trigger overrun error has occurred
Result Register Overrun Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read
(i.e. the old data has been lost). This flag is cleared when one of the following occurs:
A) Write “1” to FIFOR
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No overrun has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag was still set)
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,
CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO
mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence.
If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
389
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.