MC9S12G Datasheet, PDF (1109/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Electrical Characteristics
Table A-24. NVM Reliability Characteristics
Conditions are shown in Table A-11 unless otherwise noted
NUM C
Rating
Symbol Min
Typ
Max Unit
Program Flash Arrays
1 C Data retention at an average junction temperature of T_Javg = 85°C¹ t_NVMRET 20
100²
—
Years
after up to 10,000 program/erase cycles
2 C Program Flash number of program/erase cycles
(-40°C ≤ Tj ≤ 150°C)
n_FLPE
10K
100K³
—
Cycles
EEPROM Array
3 C Data retention at an average junction temperature of T_Javg = 85°C¹ t_NVMRET 5
after up to 100,000 program/erase cycles
100²
—
Years
4 C Data retention at an average junction temperature of T_Javg = 85°C¹ t_NVMRET 10
100²
—
Years
after up to 10,000 program/erase cycles
5 C Data retention at an average junction temperature of T_Javg = 85°C¹ t_NVMRET 20
100²
—
Years
after less than 100 program/erase cycles
6 C EEPROM number of program/erase cycles (-40°C ≤ Tj ≤ 150°C)
n_FLPE 100K 500K³
—
Cycles
1 _{TJavg does not exceed 85°C in a typical temperature profile over the lifetime of a consumer, industrial or automotive application.}
2 _{Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to}
25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to
Engineering Bulletin EB618
3 _{Spec table quotes typical endurance evaluated at 25°C for this product family. For additional information on how Freescale defines}
Typical Endurance, please refer to Engineering Bulletin EB619.
A.7 Phase Locked Loop
A.7.1 Jitter Definitions
With each transition of the feedback clock, the deviation from the reference clock is measured and input
voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes
in the VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure A-3.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
1109
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.