MC9S12G Datasheet, PDF (403/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B12CV2)
Table 12-2. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1_{If only AN0 should be converted use MULT=0.}
AN6
AN7
AN8
AN9
AN10
AN11
AN11
AN11
AN11
AN11
12.3.2.2 ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Module Base + 0x0001
7
R
ETRIGSEL
W
Reset
0
6
SRES1
5
SRES0
4
3
2
1
0
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
0
1
0
1
1
1
1
Figure 12-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime
Write: Anytime
Table 12-3. ATDCTL1 Field Descriptions
Field
Description
7
ETRIGSEL
6–5
SRES[1:0]
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 12-5.
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 12-4 for
coding.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
403
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.