MC9S12G Datasheet, PDF (245/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12G Memory Map Controller (S12GMMCV1)
Table 5-8. Global Address Ranges
S12GN16
0x04000-
0x07FFF
(NVMRES=1)
0x04000-
0x07FFF
(NVMRES=0)
0x08000-
0x0FFFF
0x08000-
0x1FFFF
0x20000-
0x27FFF
0x28000-
0x2FFFF
0x30000-
0x33FFF
0x34000-
0x37FFF
0x38000-
0x3BFFF
0x3C000-
0x3FFFF
Reserved
16k
S12GN32
S12G48,
S12GN48
S12G64
S12G96 S12G128 S12G192
Internal NVM Resources (for details refert to section FTMRG)
Reserved
Unimplemented
Reserved
Reserved
Flash
32k
48k
64k
96k
128k
192k
S12G240
240k
5.4.4 Prioritization of Memory Accesses
On S12G devices, the CPU and the BDM are not able to access the memory in parallel. An arbitration
occurs whenever both modules attempt a memory access at the same time. CPU accesses are handled with
higher priority than BDM accesses unless the BDM module has been stalled for more then 128 bus cycles.
In this case the pending BDM access will be processed immediately.
5.4.5 Interrupts
The S12GMMC does not generate any interrupts.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
245
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.