MC9S12G Datasheet, PDF (332/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.1.3 S12CPMU Block Diagram
MMC
Illegal Address Access
VDDR
VSS
VDD, VDDF
(core supplies)
Low Voltage Detect VDDA
Low Voltage Detect VDDX
ILAF
LVDS
Low Voltage Interrupt
LVIE
VDDX
VSSX
Voltage
Regulator
Power-On Detect
LVRF
COP time out
S12CPMU
VDDA ^{3.13 to 5.5V}
PORF
VSSA
Power-On Reset
RESET
Clock
Monitor
External
Loop
EXTAL _Controlled
Pierce
Oscillator
XTAL _(XOSCLCP)
OSCCLK_LCP
monitor fail
UPOSC
Reset
Generator
System Reset
Oscillator status Interrupt
UPOSC=0 sets PLLSEL bit
OSCIE
OSCCLK
CAN_OSCCLK
& _{(to MSCAN)}
PLLSEL
4MHz-16MHz REFDIV[3:0] IRCTRIM[9:0]
POSTDIV[4:0]
PSTP
Reference
Divider
Internal
Reference
Clock
(IRC1M)
Post
Divider
1,2,.,32
divide
by 4
PLLCLK
ECLK2X
(Core Clock)
divide ECLK
by 2 _{(Bus Clock)}
IRCCLK
OSCE
VCOFRQ[1:0]
Lock
detect
REFCLK
FBCLK
Phase
locked
Loop with
internal
Filter (PLL)
VCOCLK
divide
by 8
(to LCD)
BDM Clock
LOCK
REFFRQ[1:0]
LOCKIE ^{PLL Lock Interrupt}
UPOSC
Divide by
2*(SYNDIV+1)
COPOSCSEL1
SYNDIV[5:0]
Bus Clock
RC ^ACLK
Osc.
Autonomous
Periodic
API_EXTCLK
Interrupt (API)
APICLK
API Interrupt
APIE
ACLK
IRCCLK
OSCCLK
COPCLK _COP
Watchdog
COP time out
to Reset
Generator _IRCCLK
COPOSCSEL0
PCE CPMUCOP
OSCCLK
RTIE ^{RTI Interrupt}
Real Time
RTICLK _{Interrupt (RTI)}
UPOSC=0 clears
RTIOSCSEL _PRE CPMURTI
Figure 10-1. Block diagram of S12CPMU
MC9S12G Family Reference Manual, Rev.1.01
332
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.