MC9S12G Datasheet, PDF (1117/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

In Table A-32 the timing characteristics for master mode are listed.
Table A-32. SPI Master Mode Timing Characteristics
Conditions are 4.5 V < V_DD35 < 5.5 V junction temperature from –40°C to +150°C.
Num C
Characteristic
Symbol
Min
Typ
1
D SCK Frequency
1
D SCK Period
2
D Enable Lead Time
3
D Enable Trail Time
4
D Clock (SCK) High or Low Time
5
D Data Setup Time (Inputs)
6
D Data Hold Time (Inputs)
9
D Data Valid after SCK Edge
10
D Data Valid after SS fall (CPHA=0)
11
D Data Hold Time (Outputs)
12
D Rise and Fall Time Inputs
13
D Rise and Fall Time Outputs
f_sck
1/2048
—
t_sck
2
—
t_L
—
1/2
t_T
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
0
—
t_rfi
—
—
t_rfo
—
—
Electrical Characteristics
Max
1/2
2048
—
—
—
—
—
15
15
—
9
9
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
A.14.2 Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
SS
(Input)
SCK
(CPOL = 0)
(Input)
SCK
(CPOL = 1)
(Input) ¹⁰
7
MISO
(Output)
2
See
Note
1
12
4
4
12
Slave MSB
9
Bit MSB-1 . . . 1
13 3
13
11
11
Slave LSB OUT
MOSI
(Input)
5
6
MSB IN
Bit MSB-1. . . 1
LSB IN
NOTE: Not defined
Figure A-8. SPI Slave Timing (CPHA = 0)
8
See
Note
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
1117
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.