MC9S12G Datasheet, PDF (503/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Writing to this register when in special modes can alter the MSCAN
functionality.
16.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 16.3.3.1,
“Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 16.4.3,
“Identifier Acceptance Filter”).
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 to Module Base + 0x0013
Access: User read/write¹
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 16-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
1 _{Read: Anytime}
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 16-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Field
7-0
AC[7:0]
Description
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Module Base + 0x0018 to Module Base + 0x001B
Access: User read/write¹
7
R
AC7
W
Reset
0
6
AC6
0
5
AC5
0
4
AC4
0
3
AC3
0
2
AC2
0
1
AC1
0
0
AC0
0
Figure 16-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
1 _{Read: Anytime}
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
503
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.