MC9S12G Datasheet, PDF (206/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Table 2-88. PIE0AD Register Field Descriptions
Field
Description
7-0 Port AD interrupt enable—
PIE0AD This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
2.4.3.62 Port AD Interrupt Enable Register (PIE1AD)
Read: Anytime
Address 0x027D
R
W
Reset
7
PIE1AD7
0
1 _{Read: Anytime}
Write: Anytime
6
PIE1AD6
5
PIE1AD5
4
PIE1AD4
3
PIE1AD3
2
PIE1AD2
0
0
0
0
0
Figure 2-61. Port AD Interrupt Enable Register (PIE1AD)
Access: User read/write¹
1
0
PIE1AD1 PIE1AD0
0
0
Table 2-89. PIE1AD Register Field Descriptions
Field
Description
7-0 Port AD interrupt enable—
PIE1AD This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
MC9S12G Family Reference Manual, Rev.1.01
206
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.