MC9S12G Datasheet, PDF (447/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

14.1.3 Block Diagram
Bus Clock
Clock
Prescaler
ETRIG0
ETRIG1
ETRIG2
ETRIG3
(See device specifi-
cation for availability
and connectivity)
Trigger
Mux
ATDCTL1
ATDDIEN
Analog-to-Digital Converter (ADC12B16CV2)
ATD Clock
Mode and
Timing Control
ATD_12B12C
Sequence Complete
Interrupt
Compare Interrupt
VDDA
VSSA
VRH
VRL
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Analog
MUX
Successive
Approximation
Register (SAR)
and DAC
Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
ATD 8
ATD 9
ATD 10
ATD 11
ATD 12
ATD 13
ATD 14
ATD 15
Sample & Hold
+
-
Comparator
Figure 14-1. ADC12B16C Block Diagram
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
447
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.