MC9S12G Datasheet, PDF (199/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.4.3.50 Port AD Data Register (PT1AD)
Address 0x0271
7
R
PT1AD7
W
6
PT1AD6
5
PT1AD5
4
PT1AD4
3
PT1AD3
2
PT1AD2
Reset
0
0
0
0
0
0
Figure 2-50. Port AD Data Register (PT1AD)
1 _{Read: Anytime. The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PT1AD1
PT1AD0
0
0
Table 2-77. PT1AD Register Field Descriptions
Field
Description
7-0
PT1AD
Port AD general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”).
2.4.3.51 Port AD Input Register (PTI0AD)
Address 0x0272 (G1, G2)
7
R PTI0AD7
W
Reset
0
Address 0x0272 (G3)
6
PTI0AD6
0
5
PTI0AD5
0
4
PTI0AD4
0
3
PTI0AD3
0
2
PTI0AD2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Never
6
5
4
3
2
0
0
0
PTI0AD3 PTI0AD2
0
0
0
0
0
Figure 2-51. Port AD Input Register (PTI0AD)
Access: User read only¹
1
PTI0AD1
0
PTI0AD0
0
0
Access: User read only¹
1
PTI0AD1
0
PTI0AD0
0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
199
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.