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MC9S12G Datasheet, PDF (508/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Figure 16-24. Receive/Transmit Message Buffer â Extended Identiï¬er Mapping (continued)
Register
Name
Bit 7
6
5
4
3
2
1
Bit0
= Unused, always read âxâ
Read:
⢠For transmit buffers, anytime when TXEx ï¬ag is set (see Section 16.3.2.7, âMSCAN Transmitter
Flag Register (CANTFLG)â) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 16.3.2.11, âMSCAN Transmit Buffer Selection Register (CANTBSEL)â).
⢠For receive buffers, only when RXF ï¬ag is set (see Section 16.3.2.5, âMSCAN Receiver Flag
Register (CANRFLG)â).
Write:
⢠For transmit buffers, anytime when TXEx ï¬ag is set (see Section 16.3.2.7, âMSCAN Transmitter
Flag Register (CANTFLG)â) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 16.3.2.11, âMSCAN Transmit Buffer Selection Register (CANTBSEL)â).
⢠Unimplemented for receive buffers.
Reset: Undeï¬ned because of RAM-based implementation
Figure 16-25. Receive/Transmit Message Buffer â Standard Identiï¬er Mapping
Register
Name
Bit 7
6
5
4
3
2
1
IDR0
0x00X0
R
W
ID10
ID9
ID8
ID7
ID6
ID5
ID4
Bit 0
ID3
IDR1
R
0x00X1 W
ID2
ID1
ID0
RTR
IDE (=0)
IDR2
R
0x00X2 W
IDR3
R
0x00X3 W
= Unused, always read âxâ
16.3.3.1 Identiï¬er Registers (IDR0âIDR3)
The identiï¬er registers for an extended format identiï¬er consist of a total of 32 bits: ID[28:0], SRR, IDE,
and RTR. The identiï¬er registers for a standard format identiï¬er consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
MC9S12G Family Reference Manual, Rev.1.01
508
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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