MC9S12G Datasheet, PDF (590/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Serial Communication Interface (S12SCIV5)
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control
register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
18.4.6.3 Data Sampling
The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust
for baud rate mismatch, the RT clock (see Figure 18-21) is re-synchronized:
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic
1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Start Bit
LSB
RXD
Samples 1 1 1 1 1 1 1 1 0
0
0
0000
Start Bit
Qualification
Start Bit
Verification
Data
Sampling
RT Clock
RT CLock Count
Reset RT Clock
Figure 18-21. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Figure 18-17 summarizes the results of the start bit verification samples.
Table 18-17. Start Bit Verification
RT3, RT5, and RT7 Samples
000
001
010
011
100
101
110
111
Start Bit Verification
Yes
Yes
Yes
No
Yes
No
No
No
Noise Flag
0
1
1
0
1
0
0
0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
MC9S12G Family Reference Manual, Rev.1.01
590
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.