MC9S12G Datasheet, PDF (610/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Serial Peripheral Interface (S12SPIV5)
19.3.2.3 SPI Baud Rate Register (SPIBR)
7
6
5
4
3
R
0
0
SPPR2
SPPR1
SPPR0
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
2
SPR2
0
Figure 19-5. SPI Baud Rate Register (SPIBR)
1
SPR1
0
0
SPR0
0
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 19-5. SPIBR Field Descriptions
Field
Description
6–4
SPPR[2:0]
2–0
SPR[2:0]
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 19-6. In master
mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 19-6. In master mode,
a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
BaudRateDivisor = (SPPR + 1) • 2^{(SPR + 1)}
The baud rate can be calculated with the following equation:
SPPR2
0
0
0
0
0
0
0
0
0
0
0
Baud Rate = BusClock / BaudRateDivisor
NOTE
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
Table 19-6. Example SPI Baud Rate Selection (25 MHz Bus Clock)
SPPR1
0
0
0
0
0
0
0
0
0
0
0
SPPR0
0
0
0
0
0
0
0
0
1
1
1
SPR2
0
0
0
0
1
1
1
1
0
0
0
SPR1
0
0
1
1
0
0
1
1
0
0
1
SPR0
0
1
0
1
0
1
0
1
0
1
0
Baud Rate
Divisor
2
4
8
16
32
64
128
256
4
8
16
Eqn. 19-1
Eqn. 19-2
Baud Rate
12.5 Mbit/s
6.25 Mbit/s
3.125 Mbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
6.25 Mbit/s
3.125 Mbit/s
1.5625 Mbit/s
MC9S12G Family Reference Manual, Rev.1.01
610
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.