MC9S12G Datasheet, PDF (400/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B12CV2)
12.2 Signal Description
This section lists all inputs to the ADC10B12C block.
12.2.1 Detailed Signal Descriptions
12.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
12.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connectivity of these inputs!
12.2.1.3 VRH, VRL
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
12.2.1.4 VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC10B12C block.
12.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC10B12C.
12.3.1 Module Memory Map
Figure 12-2 gives an overview on all ADC10B12C registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address
0x0000
0x0001
0x0002
Name
ATDCTL0
ATDCTL1
ATDCTL2
Bit 7
R
W ^Reserved
R
ETRIGSEL
W
R
0
W
6
0
SRES1
AFFC
5
4
3
2
1
Bit 0
0
0
WRAP3 WRAP2 WRAP1 WRAP0
SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
= Unimplemented or Reserved
Figure 12-2. ADC10B12C Register Summary (Sheet 1 of 3)
MC9S12G Family Reference Manual, Rev.1.01
400
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.