MC9S12G Datasheet, PDF (155/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Global Address
Register Name
0x001E
IRQCR
Table 2-20. Block Register Map (G2) (continued)
Bit 7
6
5
4
3
2
R
0
0
0
0
IRQE
IRQEN
W
1
Bit 0
0
0
0x001F
Reserved
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
0x0020–0x023F R
Non-PIM
W
Address Range
Non-PIM Address Range
0x0240
PTT
0x0241
PTIT
R
PTT7
W
R PTIT7
W
PTT6
PTIT6
PTT5
PTIT5
PTT4
PTIT4
PTT3
PTIT3
PTT2
PTIT2
PTT1
PTIT1
PTT0
PTIT0
0x0242
DDRT
R
DDRT7
W
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
0x0243
R
0
0
0
0
0
0
0
0
Reserved
W
0x0244
PERT
R
PERT7
W
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
0x0245
PPST
R
PPST7
W
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0x0246
R
0
0
0
0
0
0
0
0
Reserved
W
0x0247
R
0
0
0
0
0
0
0
0
Reserved
W
0x0248
PTS
R
PTS7
W
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
0x0249
PTIS
R PTIS7
W
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
0x024A
DDRS
0x024B
Reserved
R
DDRS7
W
R
0
W
DDRS6
0
DDRS5
0
DDRS4
0
DDRS3
0
DDRS2
0
DDRS1
0
DDRS0
0
= Unimplemented or Reserved
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
155
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.