MC9S12G Datasheet, PDF(141/1160 Page) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

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MC9S12G Datasheet, PDF (141/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

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Port Integration Module (S12GPIMV0)

Table 2-15. Port J Pins PJ7-0 (continued)

PJ1

â¢ Except 20 TSSOP and 32 LQFP: The SPI1 MOSI signal is mapped to this pin when used with the SPI

function. Depending on the conï¬guration of the enabled SPI1 the I/O state is forced to be input or

output.

â¢ 48 LQFP: The TIM channel 6 signal is mapped to this pin when used with the timer function. The TIM

forces the I/O state to be an output for a timer port associated with an enabled output.

â¢ Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.

â¢ Signal priority:

48 LQFP: MOSI1 > IOC6 > GPO

64/100 LQFP: MOSI1 > GPO

PJ0

â¢ Except 20 TSSOP and 32 LQFP: The SPI1 MISO signal is mapped to this pin when used with the SPI

function. Depending on the conï¬guration of the enabled SPI1 the I/O state is forced to be input or

output.

â¢ 48 LQFP: The PWM channel 6 signal is mapped to this pin when used with the PWM function. The

enabled PWM channel forces the I/O state to be an output.

â¢ Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.

â¢ Signal priority:

48 LQFP: MISO1 > PWM6 > GPO

64/100 LQFP: MISO1 > GPO

2.3.12

PAD15

PAD14

Pins AD15-0

NOTE

To activate the digital input function the related bit in the ADC Digital Input

Enable Register (ATDDIEN) must be set to 1. If the ADC is routed to port

C the input buffers are automatically enabled on the freed up port AD pins.

Additionally on pins shared with ACMPM and ACMPP the ACDIEN bit

must be set to 1 in the ACMP Control Register (ACMPC).

Table 2-16. Port AD Pins AD15-8

â¢ 64/100 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin

if the DAC is operating in âunbuffered DACâ mode. If this pin is used with the DAC then the digital I/O

function and pull device are disabled.

â¢ 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN15

and the related digital trigger input are mapped to this pin. The ADC function has no effect on the

output state. The input buffer is controlled by the related ATDDIEN bit and the ADC trigger function.

â¢ 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.

â¢ Signal priority:

64/100 LQFP: DACU0 > GPO

â¢ 64/100 LQFP: The non-inverting analog input signal AMPP0 of the DAC0 module is mapped to this pin

if the DAC is operating in âunbuffered DAC with operational ampliï¬erâ or âoperational ampliï¬er onlyâ

mode. If this pin is used with the DAC then the digital input buffer is disabled.

â¢ 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN14

and the related digital trigger input are mapped to this pin. The ADC function has no effect on the

output state. The input buffer is controlled by the related ATDDIEN bit and the ADC trigger function.

â¢ 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.

â¢ Signal priority:

64/100 LQFP: GPO

MC9S12G Family Reference Manual, Rev.1.01

Freescale Semiconductor

141

This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.

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