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MC9S12G Datasheet, PDF (293/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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S12S Debug Module (S12SDBG)
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 ï¬ag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding ï¬ag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These ï¬ags cannot be cleared by software, they
are cleared only when arming the module. A set ï¬ag does not inhibit the setting of other ï¬ags. Once a ï¬ag
is set, further comparator matches on the same channel in the same session have no affect on that ï¬ag.
8.3.2.8 Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module
register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data
bus compare registers, two data bus mask registers and a control register). Comparator B consists of four
register bytes (three address bus compare registers and a control register). Comparator C consists of four
register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register.
Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be
written. The control register for comparator B differs from those of comparators A and C.
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
Table 8-20. Comparator Register Layout
CONTROL
ADDRESS HIGH
ADDRESS MEDIUM
ADDRESS LOW
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
DATA HIGH MASK
DATA LOW MASK
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparator A only
Comparator A only
Comparator A only
Comparator A only
8.3.2.8.1 Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Address: 0x0028
R
W
Reset
7
SZE
0
6
5
4
3
2
1
SZ
TAG
BRK
RW
RWE
NDB
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-13. Debug Comparator Control Register DBGACTL (Comparator A)
0
COMPE
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
293
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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