MC9S12G Datasheet, PDF (122/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.2.1 Package Code
The availability of pins and the related peripheral signals are determined by a package code
(Section 2.4.3.33, “Package Code Register (PKGCR)”). The related value is loaded from a factory
programmed non-volatile memory location into the register during the reset sequence.
Based on the package code all non-bonded pins will have the input buffer disabled to avoid shoot-through
current resulting in excess current in stop mode.
2.2.2 Prioritization
If more than one output signal is attempted to be enabled on a specific pin, a priority scheme determines
the signal taking effect.
General rules:
• The peripheral with the highest amount of pins has priority on the related pins when it is enabled.
• If a peripheral can selectively disable a function, the freed up pin is used with the next enabled
peripheral signal.
• The general-purpose output function takes control if no peripheral function is enabled.
Input signals are not prioritized. Therefore the input function remains active (for example timer input
capture) even if a pin is used with the output signal of another peripheral or general-purpose output.
2.2.3 Signals and Priorities
Table 2-4 shows all pins with their related signals per device and package that are controlled by the PIM.
A signal name in squared brackets denotes the port register bit related to the digital I/O function of the pin
(port register PORT/PT not listed). It is a representative for any other port related register bit with the same
index in PTI, DDR, PER, PPS, and where applicable in PIE, PIF or WOM (see Section 2.4, “PIM Ports -
Memory Map and Register Definition”). For example pin PAD15: Signal [PT0AD7] is bit 7 of register
PT0AD; other related register bits of this pin are PTI0AD7, DDR0AD7, PER0AD7, PPS0AD7, PIE0AD7
and PIF0AD7.
NOTE
If there is more than one signal associated with a pin, the priority is indicated
by the position in the table from top (highest priority) to bottom (lowest
priority).
MC9S12G Family Reference Manual, Rev.1.01
122
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.