MC9S12G Datasheet, PDF (648/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Timer Module (TIM16B8CV3)
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
20.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
7
R
0
W
6
5
4
3
2
1
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 20-24. 16-Bit Pulse Accumulator Control Register (PACTL)
1 _{This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register}
have no functional effect. Reads from a reserved register return zeroes.
Read: Any time
Write: Any time
When PAEN is set, the Pulse Accumulator counter is enabled.The Pulse Accumulator counter shares the
input pin with IOC7.
Table 20-18. PACTL Field Descriptions
Field
6
PAEN
5
PAMOD
Description
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table 20-19.
0 Event counter mode.
1 Gated time accumulation mode.
MC9S12G Family Reference Manual, Rev.1.01
648
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.