MC9S12G Datasheet, PDF (200/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Table 2-78. PTI0AD Register Field Descriptions
Field
Description
7-0 Port AD input data—
PTI0AD A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.4.3.52 Port AD Input Register (PTI1AD)
Address 0x0273
R
W
Reset
7
PTI1AD7
0
1 _{Read: Anytime}
Write: Never
6
PTI1AD6
5
PTI1AD5
4
PTI1AD4
3
PTI1AD3
2
PTI1AD2
0
0
0
0
0
Figure 2-52. Port AD Input Register (PTI1AD)
Access: User read only¹
1
PTI1AD1
0
PTI1AD0
0
0
Table 2-79. PTI1AD Register Field Descriptions
Field
Description
7-0 Port AD input data—
PTI1AD A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.4.3.53 Port AD Data Direction Register (DDR0AD)
Address 0x0274 (G1, G2)
Access: User read/write¹
7
R
DDR0AD7
W
Reset
0
Address 0x0274 (G3)
6
DDR0AD6
0
5
DDR0AD5
0
4
DDR0AD4
0
3
DDR0AD3
0
2
DDR0AD2
0
1
0
DDR0AD1 DDR0AD0
0
0
Access: User read/write¹
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
1
0
0
0
0
DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0
0
0
0
0
0
0
0
Figure 2-53. Port AD Data Direction Register (DDR0AD)
MC9S12G Family Reference Manual, Rev.1.01
200
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.