MC9S12G Datasheet, PDF (417/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B12CV2)
Table 12-22. Conversion result mapping to ATDDRn
A/D
resolution
DJM
conversion result mapping to ATDDRn
8-bit data 1
Result-Bit[11:8]=0000,
Result-Bit[7:0] = conversion result
10-bit data 1
Result-Bit[11:10]=00,
Result-Bit[9:0] = conversion result
12.4 Functional Description
The ADC10B12C consists of an analog sub-block and a digital sub-block.
12.4.1 Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.
12.4.1.1 Sample and Hold Machine
The Sample and Hold Machine controls the storage and charge of the sample capacitor to the voltage level
of the analog signal at the selected ADC input channel.
During the sample process the analog input connects directly to the storage node.
The input analog signals are unipolar and must be within the potential range of VSSA to VDDA.
During the hold process the analog input is disconnected from the storage node.
12.4.1.2 Analog Input Multiplexer
The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold
machine.
12.4.1.3 Analog-to-Digital (A/D) Machine
The A/D Machine performs analog to digital conversions. The resolution is program selectable to be either
8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the
sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary
search algorithm, the A/D machine identifies the discrete voltage that is nearest to the sampled and stored
voltage.
When not converting the A/D machine is automatically powered down.
Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result
in a non-railed digital output code.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
417
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.