MC9S12G Datasheet, PDF (607/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Serial Peripheral Interface (S12SPIV5)
Register
Name
Bit 7
6
5
4
3
2
SPIDRL R R7
R6
R5
R4
R3
R2
W
T7
T6
T5
T4
T3
T2
Reserved R
W
Reserved R
W
= Unimplemented or Reserved
Figure 19-2. SPI Register Summary
1
Bit 0
R1
R0
T1
T0
19.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
19.3.2.1 SPI Control Register 1 (SPICR1)
R
W
Reset
7
SPIE
0
6
SPE
5
SPTIE
4
MSTR
3
CPOL
2
CPHA
0
0
0
0
1
Figure 19-3. SPI Control Register 1 (SPICR1)
1
SSOE
0
0
LSBFE
0
Read: Anytime
Write: Anytime
Table 19-1. SPICR1 Field Descriptions
Field
7
SPIE
6
SPE
5
SPTIE
4
MSTR
Description
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
607
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.