MC9S12G Datasheet, PDF (209/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.5.2.1 Data Register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general-purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general-purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to 0.
If the data direction register bits are set to 1, the contents of the data register is returned. This is independent
of any other configuration (Figure 2-64).
2.5.2.2 Input Register (PTIx)
This register is read-only and always returns the buffered state of the pin (Figure 2-64).
2.5.2.3 Data Direction Register (DDRx)
This register defines whether the pin is used as an general-purpose input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-64).
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (2.5.2.1/2-209).
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
PTI
0
1
PT
0
1
PIN
DDR
0
1
data out
Module _{output enable}
module enable
Figure 2-64. Illustration of I/O pin functionality
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
209
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.