MC9S12G Datasheet, PDF (333/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Figure 10-2 shows a block diagram of the XOSCLCP.
S12 Clock, Reset and Power Management Unit (S12CPMU)
Peak
Detector
OSCCLK_LCP
Gain Control
Clock
Monitor
monitor fail
VDD = 1.8 V
VSS
Rf
EXTAL
Quartz Crystals
or
Ceramic Resonators
XTAL
C1
C2
VSS
VSS
Figure 10-2. XOSCLCP Block Diagram
10.2 Signal Description
This section lists and describes the signals that connect off chip.
10.2.1 RESET
Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
10.2.2 EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If
XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If
OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 kΩ and the XTAL
pin is pulled down by an internal resistor of approximately 700 kΩ.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
333
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.