MC9S12G Datasheet, PDF (169/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Table 2-28. DDRC Register Field Descriptions
Field
7-0
DDRC
Description
Port C Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.8 Port D Data Direction Register (DDRD)
Address 0x0007 (G1)
7
R
DDRD7
W
6
DDRD6
Reset
0
0
Address 0x0007 (G2, G3)
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-9. Port D Data Direction Register (DDRD)
Access: User read/write¹
1
0
DDRD1
DDRD0
0
0
Access: User read only
1
0
0
0
0
0
Table 2-29. DDRD Register Field Descriptions
Field
7-0
DDRD
Description
Port D Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.9 Port E Data Register (PORTE)
Address 0x0008
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-10. Port E Data Register (PORTE)
Access: User read/write¹
1
0
PE1
PE0
0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
169
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.