MC9S12G Datasheet, PDF (1122/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Detailed Register Address Map
0x001A–0x001B Device ID Register (PARTIDH/PARTIDL)
Address Name
Bit 7
0x001A
0x001B
R
PARTIDH
W
R
PARTIDL
W
Bit 6
Bit 5
Bit 4
Bit 3
PARTIDH
PARTIDL
Bit 2
Bit 1
Bit 0
0x001C–0x001F Port Integration Module (PIM) Map 3 of 6
Address Name
0x001C ECLKCTL
0x001D Reserved
0x001E IRQCR
0x001F Reserved
Bit 7
R
NECLK
W
R
0
W
R
IRQE
W
R
0
W
Bit 6
NCLKX2
0
IRQEN
0
Bit 5
DIV16
0
0
0
Bit 4
EDIV4
0
0
0
Bit 3
EDIV3
0
0
0
Bit 2
EDIV2
0
0
0
Bit 1
EDIV1
0
0
0
Bit 0
EDIV0
0
0
0
0x0020–0x002F Debug Module (DBG)
Address
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0028
Name
DBGC1
DBGSR
DBGTCR
DBGC2
DBGTBH
DBGTBL
DBGCNT
DBGSCRX
DBGMFR
DBGACTL
DBGBCTL
DBGCCTL
Bit 7
R
ARM
W
R TBF
W
R
0
W
R
0
W
R Bit 15
W
R Bit 7
W
R ¹ TBF
W
R
0
W
R
0
W
R
SZE
W
R
SZE
W
R
0
W
Bit 6
0
TRIG
0
TSOURCE
0
Bit 14
Bit 6
0
0
0
SZ
SZ
0
Bit 5
0
0
0
0
Bit 13
Bit 5
0
0
TAG
TAG
TAG
Bit 4
BDM
0
Bit 3
DBGBRK
0
Bit 2
0
SSF2
0
TRCMOD
0
0
0
Bit 12
Bit 11
Bit 10
Bit 4
Bit 3
Bit 2
CNT
0
SC3
SC2
0
0
MC2
BRK
RW
RWE
BRK
RW
RWE
BRK
RW
RWE
Bit 1
Bit 0
COMRV
SSF1
SSF0
0
TALIGN
ABCM
Bit 9
Bit 8
Bit 1
Bit 0
SC1
MC1
SC0
MC0
NDB
0
0
COMPE
COMPE
COMPE
MC9S12G Family Reference Manual, Rev.1.01
1122
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.