MC9S12G Datasheet, PDF (1099/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Electrical Characteristics
A.5 DAC Characteristics
This section describes the electrical characteristics of the digital to analog converter.
Table A-22. Static Electrical Characteristics - DAC_8B5V
Characteristics noted under conditions 3.13V <= VDDA <= 5.5V>, -40˚C < Tj < 150˚C >, VRH=VDDA, VRL=VSSA
unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A = 25˚C under nominal
conditions unless otherwise noted.
Num C
Ratings
Symbol
Min
Typ
Max
Unit
1
Supply Current of DAC_8B5V
D buffer disabled
P buffer enabled
2
Reference current
D reference disabled
P reference enabled
3 D Resolution
4 C Relative Accuracy
@ amplifier output
5 P Differential Nonlinearity @ amplifier output
6 D DAC Range A (FVR bit = 1)
7 D DAC Range B (FVR bit = 0
8 C Output Voltage
unbuffered range A or B (load >= 50MΩ)
9 P Output Voltage (DRIVE bit = 0)¹
buffered range A (load >= 100KΩ to VSSA)
buffered range A (load >= 100KΩ to VDDA)
buffered range B (load >= 100KΩ to VSSA)
buffered range B (load >= 100KΩ to VDDA)
10 P Output Voltage (DRIVE bit = 1)²
buffered range B with 6.4KΩ load into resistor
divider of 800Ω /6.56KΩ between VDDA and
VSSA.
(equivalent load is >= 65KΩ to VSSA) or
(equivalent load is >= 7.5KΩ to VDDA)
11 D Buffer Output Capacitive load
12 P Buffer Output Offset
13 P Settling time
14 D Reverence voltage high
1 _{DRIVE bit = 1 is not recomended in this case.}
2 _{DRIVE bit = 0 is not allowed with this high load.}
I_buf
I_ref
INL
DNL
V_out
V_out
V_out
V_out
V_out
C_load
V_offset
t_delay
V_refh
-
-
5
µA
200
600
1000
-
-
1
µA
50
150
8
bit
-0.5
+0.5
LSB
-0.5
+0.5
LSB
0...255/256(VRH-VRL)+VRL
V
32...287/320(VRH-VRL)+VRL
V
full DAC Range A or B
V
0
-
VDDA-0.15
0.15
-
VDDA
V
full DAC Range B
full DAC Range B
V
0
-
100
pF
-30
-
+30
mV
-
3
5
µs
VDDA-0.1V VDDA VDDA+0.1V V
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
1099
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.