MC9S12G Datasheet, PDF (639/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

20.3.2.3 Output Compare 7 Mask Register (OC7M)
Timer Module (TIM16B8CV3)
7
R
OC7M7
W
6
OC7M6
5
OC7M5
4
OC7M4
3
OC7M3
2
OC7M2
1
OC7M1
0
OC7M0
Reset
0
0
0
0
0
0
0
0
Figure 20-8. Output Compare 7 Mask Register (OC7M)
1 _{This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register}
have no functional effect. Reads from a reserved register return zeroes.
Read: Anytime
Write: Anytime
Table 20-4. OC7M Field Descriptions
Field
Description
7:0
OC7M[7:0]
Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,
the output compare action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
a channel 7 event, even if the corresponding pin is setup for output compare.
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
channel 7 event.
Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to
be transferred from the output compare 7 data register to the timer port.
20.3.2.4 Output Compare 7 Data Register (OC7D)
7
R
OC7D7
W
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
1
OC7D1
0
OC7D0
Reset
0
0
0
0
0
0
0
0
Figure 20-9. Output Compare 7 Data Register (OC7D)
1 _{This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register}
have no functional effect. Reads from a reserved register return zeroes.
Read: Anytime
Write: Anytime
Table 20-5. OC7D Field Descriptions
Field
Description
7:0
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
OC7D[7:0] successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
639
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.