MC9S12G Datasheet, PDF (307/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
• Destination address of RTI, RTS, and RTC instructions
• Vector address of interrupts, except for BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
Stored information includes the full 18-bit address bus and information bits, which contains a
source/destination bit to indicate whether the stored address was a source address or destination address.
NOTE
When a COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets executed after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LDX
MARK1 JMP
MARK2 NOP
#SUB_1
0,X
; IRQ interrupt occurs during execution of this
;
SUB_1
ADDR1
BRN
NOP
DBNE
*
A,PART5
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB
#$F0
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
STAB
VAR_C1
RTI
;
The execution flow taking into account the IRQ is as follows
LDX
#SUB_1
MARK1 JMP
0,X
;
IRQ_ISR LDAB
#$F0
;
STAB
VAR_C1
RTI
;
SUB_1 BRN
*
NOP
;
ADDR1 DBNE
A,PART5
;
8.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
307
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.