MC9S12G Datasheet, PDF (302/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
Table 8-32. Comparator B Access Size Considerations
Condition For Valid Match
Word accesses of ADDR[n] only
Comp B Address RWE SZE SZ8
ADDR[n]
0
1
0
Byte accesses of ADDR[n] only
ADDR[n]
0
1
1
1 _{A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.}
The comparator address register must contain the exact address from the code.
Examples
MOVW #$WORD ADDR[n]
LDD ADDR[n]
MOVB #$BYTE ADDR[n]
LDAB ADDR[n]
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in Table 8-31.
8.4.2.1.3 Comparator A
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table 8-33 lists access considerations with data bus comparison. On word accesses the data byte of the
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in Table 8-31.
Table 8-33. Comparator A Matches When Accessing ADDR[n]
SZE
SZ
DBGADHM,
DBGADLM
Access
DH=DBGADH, DL=DBGADL
0
X
0
X
0
X
$0000
$FF00
$00FF
Byte
Word
Byte, data(ADDR[n])=DH
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
0
X
0
X
0
X
$00FF
$FFFF
$FFFF
Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL
1
0
1
0
1
0
$0000
$00FF
$FF00
Word
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
1
0
1
1
1
1
$FFFF
$0000
$FF00
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte
Byte, data(ADDR[n])=DH
Comment
No databus comparison
Match data( ADDR[n])
Match data( ADDR[n+1])
Possible unintended match
Match data( ADDR[n], ADDR[n+1])
Possible unintended match
No databus comparison
Match only data at ADDR[n+1]
Match only data at ADDR[n]
Match data at ADDR[n] & ADDR[n+1]
No databus comparison
Match data at ADDR[n]
8.4.2.1.4 Comparator A Data Bus Comparison NDB Dependency
Comparator A features an NDB control bit, which allows data bus comparators to be configured to either
trigger on equivalence or trigger on difference. This allows monitoring of a difference in the contents of
an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A
MC9S12G Family Reference Manual, Rev.1.01
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Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.