MC9S12G Datasheet, PDF (295/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
Table 8-21. DBGXCTL Field Descriptions
Field
Description
3
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
RW
associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same
register is set.
0 Write cycle is matched1Read cycle is matched
2
RWE
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator.This bit is ignored if the TAG bit in the same register is set
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
1
NDB
(Comparator A)
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same
register is set. This bit is only available for comparator A.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
0
COMPE
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
Table 8-22 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the
corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution
stage of the instruction queue.
Table 8-22. Read or Write Comparison Logic Table
RWE Bit
0
0
1
1
1
1
RW Bit
x
x
0
0
1
1
RW Signal
0
1
0
1
0
1
Comment
RW not used in comparison
RW not used in comparison
Write data bus
No match
No match
Read data bus
8.3.2.8.2 Debug Comparator Address High Register (DBGXAH)
Address: 0x0029
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
0
0
Bit 17
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-16. Debug Comparator Address High Register (DBGXAH)
0
Bit 16
0
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window
from 0x0028 to 0x002F as shown in Section Table 8-23., “Comparator Address Register Visibility
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
295
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.